The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2018
Filed:
Sep. 20, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Avinash N. Ananthakrishnan, Hillsboro, OR (US);
Efraim Rotem, Haifa, IL;
Eliezer Weissmann, Haifa, IL;
Doron Rajwan, Rishon Le-Zion, IL;
Nadav Shulman, Tel Mond, IL;
Alon Naveh, Ramat Hasharon, IL;
Hisham Abu-Salah, Majdal Shams, IL;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 1/32 (2006.01); G06F 12/084 (2016.01); G06F 12/0864 (2016.01); G06F 1/28 (2006.01); G06F 12/0802 (2016.01); G06F 12/0846 (2016.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); G06F 1/28 (2013.01); G06F 1/3287 (2013.01); G06F 12/0802 (2013.01); G06F 12/084 (2013.01); G06F 12/0848 (2013.01); G06F 12/0864 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/282 (2013.01); G06F 2212/502 (2013.01); G06F 2212/621 (2013.01); Y02D 10/13 (2018.01);
Abstract
In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.