The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2018
Filed:
Mar. 20, 2017
Xilinx, Inc., San Jose, CA (US);
Banadappa V. Shivaray, Yadgiri, IN;
Ahmad R. Ansari, San Jose, CA (US);
Sanjeeva R. Duggampudi, Hyderabad, IN;
Pramod Surathkal, Hyderabad, IN;
Ushasri Merugu, Puppalguda, IN;
Bommana S. Rao, Hyderabad, IN;
Sowmya Sheela Thati, Hyderabad, IN;
Shashidhar S. Krishnamurthy, Hyderabad, IN;
XILINX, INC., San Jose, CA (US);
Abstract
Disclosed circuitry includes input-output pads, receive flip-flops, and transmit flip-flops coupled to the input-output pads. Data path control circuitry is coupled to data path control flip-flops, the receive flip-flops and the transmit flip-flops. The data path control circuitry is configured to selectably couple the receive flip-flops and the transmit flip-flops to the input-output pads in response to states of the data path control flip-flops. Clock control circuitry is coupled to clock control flip-flops, the receive flip-flops and the transmit flip-flops. The clock control circuitry is configured to selectably apply one of multiple clock signals to the receive flip-flops and the transmit flip-flops in response to states of the clock control flip-flops. A first scan chain is coupled to the clock control flip-flops and the data path control flip-flops. A second scan chain is coupled to the receive flip-flops and the transmit flip-flops.