The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2018
Filed:
Dec. 26, 2015
Applicant:
Intel Ip Corporation, Santa Clara, CA (US);
Inventors:
Kenan Kocagoez, Nuremberg, DE;
Johannes Brendel, Erlangen, DE;
Assignee:
Intel IP Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04W 52/02 (2009.01); G06F 1/20 (2006.01); G06F 1/32 (2006.01); H04W 24/04 (2009.01);
U.S. Cl.
CPC ...
H04W 52/0261 (2013.01); G06F 1/203 (2013.01); G06F 1/206 (2013.01); G06F 1/3209 (2013.01); H04W 24/04 (2013.01); Y02D 70/00 (2018.01); Y02D 70/1262 (2018.01); Y02D 70/142 (2018.01); Y02D 70/144 (2018.01); Y02D 70/164 (2018.01); Y02D 70/166 (2018.01); Y02D 70/168 (2018.01); Y02D 70/26 (2018.01);
Abstract
Described herein are technologies related to an implementation of a thermal management scheme in a device. Particularly, a look up table or LUT is configured to include a data set of information (e.g., user-profile data, network-profile data) and a corresponding recommended thermal throttling mode. During regular device operation, conditions internal/external to the device is detected and the corresponding thermal throttling mode (from the LUT) is applied. In certain implementations, optimization algorithms are used in place of the LUT.