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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10062764 B1

PDFFull Text
Date of Patent:
Aug. 28, 2018

Filed:

Jul. 31, 2017

Semiconductor device having void between gate electrode and sidewall spacer and manufacturing method thereof

Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Yen-Liang Wu, Taipei, TW;

Wen-Tsung Chang, Tainan, TW;

Jui-Ming Yang, Taichung, TW;

I-Fan Chang, Hsinchu, TW;

Chun-Ting Chiang, Kaohsiung, TW;

Chih-Wei Lin, Kaohsiung, TW;

Bo-Yu Su, Tainan, TW;

Chi-Ju Lee, Tainan, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Attorney:

Winston Hsu

Primary Examiner:

Tom Thomas

Assistant Examiner:

Nilufa Rahm

Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 21/3213 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/515 (2013.01); H01L 21/28088 (2013.01); H01L 21/32139 (2013.01); H01L 29/0649 (2013.01); H01L 29/42368 (2013.01); H01L 29/42376 (2013.01); H01L 29/4966 (2013.01); H01L 29/0847 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66568 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.

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