Silicon-on-insulator (soi) complementary metal oxide semiconductor (cmos) standard library cell circuits having a gate back-bias rail(s), and related systems and methods

Abstract

Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having gate back-bias rail(s) are disclosed. Related systems and methods are also disclosed. In one aspect, a SOI CMOS standard library cell circuit is provided that is comprised of one or more standard library cells. Each standard library cell includes one or more PMOS channel regions and one or more NMOS channel regions. Each standard library cell has one or more gate back-bias rails disposed adjacent to PMOS and NMOS channel regions. The gate back-bias rails are configured to apply bias voltages to corresponding PMOS and NMOS channel regions to adjust threshold voltages of PMOS and NMOS transistors associated with the PMOS and NMOS channel regions, respectively. Voltage biasing can be controlled to adjust timing of an IC using SOI CMOS standard library cell circuits to achieve design timing targets without including timing closure elements that consume additional area.