The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2018
Filed:
Dec. 30, 2016
Applicant:
Ememory Technology Inc., Hsinchu, TW;
Inventor:
Po-Hao Huang, Hsinchu, TW;
Assignee:
eMemory Technology Inc., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/18 (2006.01); G11C 17/16 (2006.01); G06F 12/14 (2006.01); H04L 9/32 (2006.01); G11C 29/00 (2006.01); G11C 16/22 (2006.01); G11C 7/24 (2006.01); G06F 21/73 (2013.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G06F 21/72 (2013.01); H03K 3/356 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 5/06 (2006.01); H01L 27/112 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0673 (2013.01); G06F 11/1076 (2013.01); G06F 12/1408 (2013.01); G06F 21/72 (2013.01); G06F 21/73 (2013.01); G11C 7/10 (2013.01); G11C 7/22 (2013.01); G11C 7/24 (2013.01); G11C 16/0408 (2013.01); G11C 16/08 (2013.01); G11C 16/22 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 17/16 (2013.01); G11C 29/785 (2013.01); H03K 3/356113 (2013.01); H04L 9/3278 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/402 (2013.01); G11C 5/063 (2013.01); H01L 27/11206 (2013.01);
Abstract
A circuit architecture for operating error-correction code (ECC) in a memory apparatus includes a control circuit and an ECC circuit. The ECC circuit is coupled with the control circuit. The control circuit receives a first data of a set of bits to invert the first data as an inverted data. The ECC circuit receives the inverted data for encryption or decryption and outputs an ECC-processed data. The control circuit inverts the ECC-processed data as a second data.
Huang, Po-Hao. (2018). Memory architecture with ecc and method for operating memory with ecc (U.S. Patent No. 10062446). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10062446
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile