The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2018

Filed:

Sep. 25, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David Pardo Keppel, Seattle, WA (US);

Denis M. Khartikov, San Jose, CA (US);

Fernando LaTorre, Barcelona, ES;

Marc Lupon, Barcelona, ES;

Grigorios Magklis, Barcelona, ES;

Naveen Neelakantam, Mountain View, CA (US);

Georgios Tournavitis, Barcelona, ES;

Polychronis Xekalakis, Barcelona, ES;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30185 (2013.01); G06F 9/384 (2013.01); G06F 9/3857 (2013.01);
Abstract

A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.


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