The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2018
Filed:
Aug. 31, 2017
Xilinx, Inc., San Jose, CA (US);
Hong Shi, Fremont, CA (US);
Siow Chek Tan, Los Gatos, CA (US);
Sarajuddin Niazi, Union City, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
An interface layout for a vertical interface of a first semiconductor component is disclosed. A first one or more conductors configured to carry power signals extends vertically from the first semiconductor component. A second one or more conductors configured to carry data signals extends vertically from the first semiconductor component. A third one or more conductors configured to carry ground signals extending vertically from the first semiconductor component. The first one or more conductors are further configured to shield and separate the second one or more conductors. A fourth one or more conductors extends horizontally from the first one or more conductors adjacent to and terminating proximal to the third one or more conductors. A fifth one or more conductors extending horizontally from the third one or more conductors adjacent to and terminating proximal to the first one or more conductors and the fourth one or more conductors. The fourth one or more conductors and the corresponding adjacent fifth one or more conductors form a plate capacitor.