The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Nov. 30, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Josephine B. Chang, Mahopac, NY (US);

Isaac Lauer, Yorktown Heights, NY (US);

Chung-Hsun Lin, White Plains, NY (US);

Jeffrey W. Sleight, Ridgefield, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/775 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 29/06 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 21/308 (2013.01); H01L 21/30604 (2013.01); H01L 21/31051 (2013.01); H01L 21/31111 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66636 (2013.01); H01L 29/66742 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01);
Abstract

At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.


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