The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Apr. 11, 2017
Applicant:

Delta Electronics, Inc., Taoyuan, TW;

Inventors:

Chia-Yen Lee, Taoyuan, TW;

Hsin-Chang Tsai, Taoyuan, TW;

Peng-Hsin Lee, Taoyuan, TW;

Shiau-Shi Lin, Taoyuan, TW;

Tzu-Hsuan Cheng, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49586 (2013.01); H01L 23/29 (2013.01); H01L 23/3114 (2013.01); H01L 23/49575 (2013.01); H01L 24/09 (2013.01); H01L 24/49 (2013.01); H01L 25/0655 (2013.01); H01L 2224/0233 (2013.01); H01L 2224/40245 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/49105 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/19105 (2013.01);
Abstract

A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.


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