The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2018
Filed:
Jun. 20, 2016
Applicant:
Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;
Inventors:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823842 (2013.01); H01L 21/265 (2013.01); H01L 21/28088 (2013.01); H01L 21/28097 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 27/1104 (2013.01); H01L 29/4966 (2013.01); H01L 29/4975 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract
A method for forming a transistor is provided. The method includes providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate. The dielectric layer has a gate structure recess. The method also includes forming a work function layer on a bottom and sidewalls of the gate structure recess; performing an ion implantation on the work function layer; and forming a gate layer on the work function layer after the ion implantation.