The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

Dec. 07, 2012
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Huilong Zhu, Poughkeepsie, NY (US);

Qiuxia Xu, Beijing, CN;

Yanbo Zhang, Beijing, CN;

Hong Yang, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/266 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/268 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28008 (2013.01); H01L 21/265 (2013.01); H01L 21/266 (2013.01); H01L 21/28088 (2013.01); H01L 21/28167 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/4983 (2013.01); H01L 29/51 (2013.01); H01L 29/513 (2013.01); H01L 29/6659 (2013.01); H01L 29/66545 (2013.01); H01L 29/78 (2013.01); H01L 29/7833 (2013.01); H01L 21/268 (2013.01); H01L 21/26513 (2013.01); H01L 29/517 (2013.01);
Abstract

Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer.


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