The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2018

Filed:

May. 11, 2016
Applicant:

Dspace Digital Signal Processing and Control Engineering Gmbh, Paderborn, DE;

Inventors:

Jochen Sauer, Brakel, DE;

Robert Leinfellner, Paderborn, DE;

Matthias Klemm, Paderborn, DE;

Thorsten Brehm, Paderborn, DE;

Robert Polnau, Paderborn, DE;

Matthias Schmitz, Paderborn, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/10 (2006.01); G06F 13/12 (2006.01); G06F 13/20 (2006.01); G06F 13/40 (2006.01); G06F 9/445 (2018.01); G06F 15/78 (2006.01); G11C 8/18 (2006.01); G06F 13/38 (2006.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 13/102 (2013.01); G06F 9/44505 (2013.01); G06F 13/126 (2013.01); G06F 13/20 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G06F 13/4072 (2013.01); G06F 15/7885 (2013.01); G11C 8/18 (2013.01); G06F 9/4411 (2013.01); G06F 13/385 (2013.01);
Abstract

A method for configuring an interface unit of a computer system with a first processor and a second processor stored in the interface unit. A data link is set up between the first processor and the second processor. A peripheral of the computer system is configured to store input data in an input data channel and to read output data from an output data channel, and the second processor is configured to read the input data from the input data channel and to store output data in the output data channel. A sequence of processor commands for the second processor is created such that a number of subsequences is created.


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