The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2018
Filed:
Aug. 02, 2017
Applicant:
Opto Tech Corporation, Hsinchu, TW;
Inventors:
Assignee:
OPTO TECH CORPORATION, Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 29/8605 (2006.01); G11C 13/00 (2006.01); H01L 29/267 (2006.01); H01L 29/417 (2006.01); H01L 33/00 (2010.01);
U.S. Cl.
CPC ...
H01L 29/8605 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H01L 29/267 (2013.01); H01L 29/417 (2013.01); G11C 2013/005 (2013.01); G11C 2013/009 (2013.01); G11C 2213/33 (2013.01); G11C 2213/34 (2013.01); G11C 2213/54 (2013.01); H01L 33/002 (2013.01);
Abstract
A resistive memory element includes a P-type layer, a tunneling structure and an N-type layer. The tunneling structure is formed on the P-type layer. The N-type layer is formed on the tunneling structure. When a bias voltage higher than a reset voltage is applied to the P-type layer and the N-type layer, the resistive memory element is in a reset state. When the bias voltage lower than a set voltage is applied to the P-type layer and the N-type layer, the resistive memory element is in a set state.