The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2018
Filed:
May. 18, 2017
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Yu-Lien Huang, Hsinchu County, TW;
Tsai-Chun Li, Hsinchu, TW;
Ching-Feng Fu, Taichung, TW;
Ming-Huan Tsai, Hsinchu County, TW;
D. T. Lee, Hsinchu, TW;
Cheng-Hua Yang, Zhubei, TW;
Yi-Chen Lo, Zhubei, TW;
Assignee:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/31116 (2013.01); H01L 29/4232 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01);
Abstract
A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.