The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

May. 31, 2017
Applicants:

Stmicroelectronics SA, Montrouge, FR;

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Florian Cacho, Grenoble, FR;

Vincent Huard, Le Versoud, FR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/01 (2006.01); H01L 27/092 (2006.01); H03K 3/037 (2006.01); H03K 19/21 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0928 (2013.01); H01L 29/1083 (2013.01); H03K 3/037 (2013.01); H03K 19/21 (2013.01);
Abstract

The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.


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