The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Jan. 27, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hongbin Shi, Hwaseong-si, KR;

Junho Lee, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/3128 (2013.01); H01L 23/3178 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A semiconductor package includes a lower package including a lower package substrate, a lower semiconductor chip disposed on the lower package substrate, and a lower mold layer disposed on the lower package substrate, and an upper package disposed on the lower package. The upper package includes an upper package substrate and an upper semiconductor chip disposed on the upper package substrate. The semiconductor package additionally includes connection terminals disposed between the lower and upper package substrates. The connection terminals comprise outermost connection terminals and inner connection terminals. The inner connection terminals are disposed between the lower semiconductor chip and outermost connection terminals. The semiconductor package further includes a first under-fill layer disposed between the lower package substrate and the upper package substrate. At least one of the outermost connection terminals is disposed outside of the lower mold layer.


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