The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2018
Filed:
Jan. 04, 2016
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53295 (2013.01); H01L 21/31144 (2013.01); H01L 21/76811 (2013.01); H01L 21/76813 (2013.01); H01L 21/76816 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.