The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Mar. 30, 2017
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Quan Qi, Beaverton, OR (US);

Carlton E. Hanna, Santa Clara, CA (US);

Eytan Mann, Modiin, IL;

Sidharth Dalmia, Fair Oaks, CA (US);

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/433 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4334 (2013.01); H01L 21/4814 (2013.01); H01L 23/3677 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01);
Abstract

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.


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