The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

May. 03, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventor:

Shih-Wei Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/7681 (2013.01); H01L 21/76808 (2013.01); H01L 21/76816 (2013.01); H01L 29/42376 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01); H01L 2221/1031 (2013.01);
Abstract

A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a FinFET (Field-Effect Transistor) device is provided. Then, spacers and various mask layers are formed on gate structures of the FinFET device to provide a self-alignment structure. Thereafter, source/drain contacts and gate contacts are formed in the self-alignment structure to enable the source/drain contacts to be electrically connected to the source/drain structures of the FinFET device, and enable the gate contacts to be electrically connected to the gate structures. Therefore, self-alignment is achieved.


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