The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Jan. 28, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Ching-Wen Hung, Tainan, TW;

Chih-Sen Huang, Tainan, TW;

Po-Chao Tsao, New Taipei, TW;

Chieh-Te Chen, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 23/485 (2006.01); H01L 29/66 (2006.01); H01L 21/283 (2006.01); H01L 21/321 (2006.01); H01L 23/528 (2006.01); H01L 29/45 (2006.01); H01L 29/417 (2006.01); H01L 23/532 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/283 (2013.01); H01L 21/32115 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/485 (2013.01); H01L 23/528 (2013.01); H01L 23/53209 (2013.01); H01L 29/41758 (2013.01); H01L 29/45 (2013.01); H01L 29/665 (2013.01); H01L 29/66545 (2013.01); H01L 29/66575 (2013.01); H01L 29/78 (2013.01); H01L 29/7845 (2013.01); H01L 29/7848 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 23/53295 (2013.01); H01L 29/165 (2013.01); H01L 29/41725 (2013.01); H01L 29/41783 (2013.01); H01L 29/7843 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate.


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