The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Feb. 28, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Shyam Sunder Raghunathan, Sunnyvale, CA (US);

Pranav Kalavade, San Jose, CA (US);

Krishna K. Parat, Palo Alto, CA (US);

Charan Srinivasan, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01); G11C 16/12 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/12 (2013.01); G11C 16/3427 (2013.01);
Abstract

Methods of operating a memory include applying a first voltage level to control gates of a plurality of memory cells selected to be programmed while applying a second voltage level to a respective data line for each memory cell of the plurality of memory cells; increasing the voltage level applied to the respective data line for memory cells of a first subset of memory cells to a third voltage level then increasing the voltage level applied to the control gates of the plurality of memory cells to a fourth voltage level; increasing the voltage level applied to the respective data line for each memory cell of a second subset of memory cells of the plurality of memory cells to a fifth voltage level then; and after increasing the voltage level applied to the respective data line for each memory cell of the second subset of memory cells to the fifth voltage level, increasing the voltage level applied to the control gates of the plurality of memory cells to a sixth voltage level.


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