The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2018

Filed:

Jul. 19, 2016
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Sundar Iyer, Palo Alto, CA (US);

Shang-Tse Chuang, Los Altos, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 12/08 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0629 (2013.01); G06F 3/0604 (2013.01); G06F 3/0652 (2013.01); G06F 3/0673 (2013.01); G06F 12/08 (2013.01); G06F 2212/254 (2013.01);
Abstract

A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed. Each algorithmic memory block includes a memory controller that implements a specific storage algorithm and a set of lower level memory components. Each of those lower level memory components may be constructed with another algorithmic memory block or with a fundamental memory block. By organizing algorithmic memory blocks in various different hierarchical organizations, may different complex memory systems that provide new features may be created.


Find Patent Forward Citations

Loading…