The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2018
Filed:
Aug. 23, 2017
Intel Corporation, Santa Clara, CA (US);
Vedaraman Geetha, Fremont, CA (US);
Henk G. Neefs, Palo Alto, CA (US);
Brian S. Morris, Santa Clara, CA (US);
Sreenivas Mandava, Los Altos, CA (US);
Massimo Sutera, Sunnyvale, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.