The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2018
Filed:
Feb. 06, 2014
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Paul Y. Wu, Saratoga, CA (US);
Sarajuddin Niazi, Union City, CA (US);
Raymond E. Anderson, Santa Cruz, CA (US);
Suresh Ramalingam, Fremont, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/14 (2006.01); H01R 12/71 (2011.01); H01R 43/02 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01R 12/71 (2013.01); H01L 23/5385 (2013.01); H01R 43/0235 (2013.01); H01L 23/49816 (2013.01); H01L 23/5386 (2013.01); H01L 2224/16 (2013.01); H01L 2924/0002 (2013.01); Y10T 29/49117 (2015.01);
Abstract
An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.