The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Dec. 20, 2016
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Wein-Town Sun, Taoyuan, TW;

Wei-Ren Chen, Pingtung County, TW;

Ying-Je Chen, Taichung, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11558 (2017.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 27/11524 (2017.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11558 (2013.01); H01L 27/11524 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/42328 (2013.01);
Abstract

A single-poly nonvolatile memory cell includes an SOI substrate having a semiconductor layer, a first OD region and a second OD region on the semiconductor layer, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor disposed on the first OD region. The PMOS floating gate transistor is serially connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension is continuously extended from the floating gate to the second OD region and is capacitively coupled to the second OD region.


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