The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Jun. 18, 2015
Applicants:

Prasoonkumar Surti, Folsom, CA (US);

Thomas Piazza, Granite Bay, CA (US);

Abhishek R. Appu, El Dorado Hills, CA (US);

Inventors:

Prasoonkumar Surti, Folsom, CA (US);

Thomas Piazza, Granite Bay, CA (US);

Abhishek R. Appu, El Dorado Hills, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/00 (2006.01); G06T 15/00 (2011.01); G06T 11/40 (2006.01); G06T 7/13 (2017.01);
U.S. Cl.
CPC ...
G06T 15/005 (2013.01); G06T 7/13 (2017.01); G06T 11/40 (2013.01); G06T 2210/12 (2013.01);
Abstract

In embodiments described herein, graphics hardware is described to reduce the number of wasted clock cycles expended during rasterization and performs coverage test iteration in a cache coherent manner. An exemplary embodiment comprises block selection logic to select an initial block of pixels associated with edges of a primitive and edge determination logic to analyze the initial block of pixels to determine a set of fully covered quadrants of the initial block of pixels and analyze a block of pixels adjacent to the initial block of pixels to determine whether the block of adjacent pixels is void.


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