The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Jun. 28, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Hugh Wilkinson, Newton, MA (US);

James C. Wright, Sewell, NJ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/12 (2006.01); H04L 12/931 (2013.01); H04L 12/741 (2013.01); H04L 12/933 (2013.01); H04L 12/937 (2013.01);
U.S. Cl.
CPC ...
H04L 49/351 (2013.01); H04L 45/74 (2013.01); H04L 49/10 (2013.01); H04L 49/254 (2013.01); H04L 49/70 (2013.01); H04L 61/6022 (2013.01);
Abstract

Examples include techniques for virtual Ethernet switching of a multi-node fabric. In some examples, first Ethernet links coupled with a group of Ethernet gateways are link aggregated. The group of Ethernet gateways couple with respective individual physical switch ports of a fabric switch of a multi-node fabric to form a default logical gateway to provide an uplink between a virtual Ethernet switch and an Ethernet network external to the multi-node fabric. Also, one or more individual Ethernet gateways coupled with respective individual physical switch ports of the fabric switch may be arranged to provide one or more respective downlinks between the virtual Ethernet switch and one or more Ethernet nodes external to the multi-node fabric via respective second Ethernet links coupled with the one or more individual Ethernet gateways.


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