The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Aug. 17, 2015
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Ethan Williford, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/26586 (2013.01); H01L 21/823412 (2013.01); H01L 21/823807 (2013.01); H01L 29/6653 (2013.01); H01L 29/6659 (2013.01); H01L 29/66484 (2013.01); H01L 29/66537 (2013.01); H01L 29/66681 (2013.01); H01L 29/7831 (2013.01);
Abstract

A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.


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