The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

May. 15, 2015
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Eng Huat Toh, Singapore, SG;

Jae Gon Lee, Daegu, KR;

Chung Foong Tan, Yishun Sapphire, SG;

Elgin Quek, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 29/42364 (2013.01); H01L 29/42368 (2013.01); H01L 29/42372 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/512 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/66681 (2013.01); H01L 29/495 (2013.01); H01L 29/513 (2013.01); H01L 29/66545 (2013.01);
Abstract

An LDMOS is formed with a second gate stack over ndrift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include a device including a substrate; a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well; a source in the first well and a drain in the second well; a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well; a first gate stack on a portion of the first well; a second gate stack on a portion of the second well, the first and second gate stacks having a common gate electrode.


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