The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Mar. 12, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Joel P. de Souza, Putnam Valley, NY (US);

Keith E. Fogel, Hopewell Junction, NY (US);

Alexander Reznicek, Troy, NY (US);

Dominic J. Schepis, Wappingers Falls, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/20 (2006.01); H01L 29/16 (2006.01); H01L 21/02 (2006.01); H01L 29/36 (2006.01);
U.S. Cl.
CPC ...
H01L 29/16 (2013.01); H01L 21/0245 (2013.01); H01L 21/02505 (2013.01); H01L 21/02513 (2013.01); H01L 21/02538 (2013.01); H01L 21/02658 (2013.01); H01L 29/36 (2013.01);
Abstract

A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the III-V layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.


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