The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Jul. 27, 2017
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Andrew E. Horch, Seattle, WA (US);

Martin L. Niset, Seattle, WA (US);

Ting-Jia Hu, Seattle, WA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/16 (2006.01); H01L 27/112 (2006.01); H01L 29/08 (2006.01); H01L 23/525 (2006.01); H01L 23/528 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); G11C 17/18 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 23/528 (2013.01); H01L 23/5252 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/42364 (2013.01);
Abstract

An OTP memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping concentration than the first doped region. A source region and a drain region of an opposite polarity are also in the semiconductor substrate. The source is positioned over the lower doped region, and the drain is positioned over the higher doped region. A plurality of anti-fuse devices, separated from each other by a portion of the lower doped region, are each positioned at least partially above a respective portion of the source region (and, in turn, above the lower doped region). A first metal line is coupled to a first subset of the anti-fuse devices, and a second metal line is coupled to a different, second subset of the anti-fuse devices arranged between the anti-fuses in the first subset.


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