The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2018
Filed:
Sep. 06, 2016
Applicant:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Inventors:
Yoichiro Kurita, Tokyo, JP;
Hideto Furuyama, Kanagawa, JP;
Hiroshi Uemura, Kanagawa, JP;
Fumitaka Ishibashi, Kanagawa, JP;
Assignee:
KABUSHIKI KAISHA TOSHIBA, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 24/94 (2013.01); H01L 24/96 (2013.01); H01L 2224/27502 (2013.01); H01L 2224/29186 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/83009 (2013.01); H01L 2224/83203 (2013.01); H01L 2224/83359 (2013.01); H01L 2224/83379 (2013.01); H01L 2224/83896 (2013.01); H01L 2924/1032 (2013.01); H01L 2924/10253 (2013.01);
Abstract
According to one embodiment, at first, a compound semiconductor layer is bonded to a position straddling a plurality of chip formation regions arranged on a substrate. One of the chip formation regions has a first size, and the compound semiconductor layer has a second size smaller than the first size. Thereafter, the compound semiconductor layer is processed to provide compound semiconductor elements on the chip formation regions. Then, the substrate is divided to correspond to the chip formation regions.