The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2018
Filed:
Jul. 28, 2016
Cadence Design Systems, Inc., San Jose, CA (US);
Praveen Kumar Chhabra, Noida, IN;
Hemant Gupta, Delhi, IN;
Sharad Gaur, Delhi, IN;
Matthew Aaron Graham, Ontario, CA;
John Laurence Rose, Longmont, CO (US);
Anupam Singal, New Delhi, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design environment including both a design under test ('DUT') and a testbench. Embodiments may further include simulating an electronic design associated with the electronic design environment and generating a coverage database associated with the electronic design. Embodiments may include performing coverage analysis of the DUT and testbench using an automated inheritance aware analysis and applying the coverage analysis results to the testbench after simulation.