The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2018
Filed:
Sep. 24, 2014
International Business Machines Corporation, Armonk, NY (US);
Robert J. Allen, Jericho, VT (US);
Yanai Danan, Austin, TX (US);
Vasant Rao, Fishkill, NY (US);
Jeffrey P. Soreff, Poughkeepsie, NY (US);
Xin Zhao, Hopewell Junction, NY (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.