The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2018

Filed:

Oct. 18, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Benjamin A. Graniello, Chandler, AZ (US);

Karthik Kumar, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 3/06 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 7/1051 (2013.01); G11C 7/22 (2013.01);
Abstract

Technology for a system operable to write and read data from memory is described. The system can include memory and a memory controller. The memory controller can send an instruction to write data to a NVM address in the memory at a time of last write (TOLW). The memory controller can determine to read the data from the NVM address in the memory at read time. The memory controller can determine a read voltage to read the data from the NVM address in the memory at the read time. The read voltage can be determined based on a difference between the TOLW and the read time, and a modeled voltage drift for the NVM address over a period of time.


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