The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2018

Filed:

Feb. 06, 2018
Applicant:

Faraday Technology Corporation, Hsinchu, TW;

Inventors:

Zhao-Yong Zhang, Hsinchu, TW;

Shih-Chin Lin, Hsinchu, TW;

Wei-Chang Wang, Hsinchu, TW;

Assignee:

Faraday Technology Corp., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/20 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
H03K 19/20 (2013.01); G06F 17/505 (2013.01);
Abstract

An arbitrating circuit includes a first NOR gate, a second NOR gate, four resistors and a pull-up circuit. The first transistor is connected with the first node and the second node, and generates a first acknowledging signal. The second transistor is connected with a supply voltage, the second node and the first transistor. The third transistor is connected with the first node and second node, and generates a second acknowledging signal. The fourth transistor is connected with the supply voltage, the first node and the third transistor. The pull-up circuit is connected with the first node, the second node, the first NOR gate and the second NOR gate. If both of the first request signal and the second request signal have a low logic level, a voltage at the second node is pulled up to a high logic level by the pull-up circuit.


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