The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2018

Filed:

Oct. 31, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventor:

Juergen Faul, Radebeul, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/02 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 23/50 (2013.01); H01L 27/0288 (2013.01);
Abstract

A method includes providing a semiconductor device structure including a substrate having a semiconductor-on-insulator (SOI) region and a hybrid region. A semiconductor device is provided in the SOI region. The semiconductor device includes a gate structure, a diode structure provided in the hybrid region and coupled to a substrate material of the SOI region, a supply circuit arrangement including first and second supply lines, a first resistor coupled between the first supply line and a first terminal of the diode structure, and a second resistor coupled between the second supply line and the substrate material positioned beneath the gate structure. At least one of the first and second resistors comprises a tunable resistor. A resistance of the tunable resistor is adjusted so as to adjust a threshold voltage (Vt) of the semiconductor device in dependence on an operating temperature of the SOI region.


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