The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2018

Filed:

Sep. 14, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Jung Hoon Kim, Gyeonggi-do, KR;

Sung Kun Park, Chungcheongbuk-do, KR;

Nam Yoon Kim, Chungcheongbuk-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11524 (2017.01); H01L 29/06 (2006.01); H01L 23/528 (2006.01); H01L 29/423 (2006.01); H01L 27/11519 (2017.01); H01L 23/535 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); H01L 23/528 (2013.01); H01L 23/535 (2013.01); H01L 27/11519 (2013.01); H01L 29/0688 (2013.01); H01L 29/42328 (2013.01); H01L 29/788 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the active region and extending in the second direction, and a selection gate intersecting the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates.


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