The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Mar. 07, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mohamed A. Abdelmoneum, Portland, OR (US);

Nasser A. Kurd, Portland, OR (US);

Amr M. Lotfy, Alexandria, EG;

Mamdouh O. Abd El-Mejeed, Alexandria, EG;

Mohamed A. Abdelsalam, Giza, EG;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01); H04L 7/033 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0331 (2013.01); H03L 7/0995 (2013.01); H04L 7/033 (2013.01);
Abstract

Described is an integrated circuit (IC) with apparatus for dynamically adapting a clock generator, e.g., phase locked loop (PLL), with respect to changes in power supply. The apparatus comprises: a voltage droop detector coupled to power supply node, the voltage droop detector to generate a digital code word representing voltage droop on the power supply node; and a PLL including a ring oscillator coupled to the power supply node, the ring oscillator to generate an output clock signal, the ring oscillator operable to adjust frequency of the output clock signal according to the digital code word.


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