The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Jul. 18, 2017
Applicant:

Palo Alto Research Center Incorporated, Palo Alto, CA (US);

Inventors:

Tse Nga Ng, Sunnyvale, CA (US);

David Eric Schwartz, San Carlos, CA (US);

Janos Veres, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 35/24 (2006.01); H01L 51/00 (2006.01); H01L 51/05 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0554 (2013.01); H01L 29/78645 (2013.01);
Abstract

A thin film device has a source region, a drain region, a first gate disposed between the source region and the drain region, a second gate disposed between the source region and the drain region, wherein the second gate region is in close proximity with the first gate region, a semiconductor film disposed between the source region, the drain region, and the first and second gate regions, and a dielectric material disposed between the source region, the drain region, the first and second gate regions, and the semiconductor film.


Find Patent Forward Citations

Ng, Tse. (2018). Circuit layout for thin film transistors in series or parallel (U.S. Patent No. 10020457). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10020457

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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