The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Apr. 25, 2017
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Khee Yong Lim, Singapore, SG;

Kian Ming Tan, Singapore, SG;

Fangxin Deng, Singapore, SG;

Zhiqiang Teo, Singapore, SG;

Xinshu Cai, Singapore, SG;

Elgin Kiok Boone Quek, Singapore, SG;

Fan Zhang, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 29/788 (2006.01); H01L 27/11573 (2017.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/11521 (2017.01); H01L 27/11548 (2017.01); H01L 27/11526 (2017.01); H01L 21/768 (2006.01); H01L 21/265 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 23/532 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); H01L 21/02236 (2013.01); H01L 21/26513 (2013.01); H01L 21/28273 (2013.01); H01L 21/32136 (2013.01); H01L 21/76816 (2013.01); H01L 21/76895 (2013.01); H01L 23/528 (2013.01); H01L 23/535 (2013.01); H01L 23/53271 (2013.01); H01L 27/11521 (2013.01); H01L 27/11526 (2013.01); H01L 27/11548 (2013.01); H01L 29/0649 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract

A method of forming a thick EG polysilicon over the FG and resulting device are provided. Embodiments include forming a CG on a substrate; forming an STI between a logic region and the CG; forming a polysilicon EG through the CG and CG HM; forming a polysilicon structure over the logic and STI; forming and overfilling with polysilicon a WL trench through the CG and CG HM, between the EG and STI; forming a buffer oxide in the polysilicon structure over the logic region and part of the STI; recessing the buffer oxide and etching back the polysilicon overfill down the CG HM; forming a second buffer oxide over the EG and logic region; recessing the WL polysilicon; removing the first and second buffer oxides; forming a mask with an opening over a center of the WL, the STI, and a majority of the logic region; and removing exposed polysilicon.


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