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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10020303 B1

PDFFull Text
Date of Patent:
Jul. 10, 2018

Filed:

Mar. 24, 2015

Methods for forming finfets having epitaxial si s/d extensions with flat top surfaces on a sige seed layer

Applicants:

International Business Machines Corporation, Armonk, NY (US);

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Hong He, Schenectady, NY (US);

Shogo Mochizuki, Tokyo, JP;

Chiahsun Tseng, Wynantskill, NY (US);

Chun-Chen Yeh, Clifton Park, NY (US);

Yunpeng Yin, Schenectady, NY (US);

Assignees:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

RENESAS ELECTRONICS CORPORATION, Kanagawa, JP;

Attorneys:

Tutunjian & Bitetto, P.C.

Vazken Alexanian

Primary Examiner:

Marc Armand

Assistant Examiner:

Younes Boulghassoul

Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 27/088 (2006.01); H01L 29/04 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/306 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/0257 (2013.01); H01L 21/02271 (2013.01); H01L 21/30604 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01);
Abstract

Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.

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