The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Sep. 04, 2014
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Edward Fuergut, Dasing, DE;

Manfred Engelhardt, Villach-Landskron, AT;

Hannes Eder, Villach-Landskron, AT;

Bernd Roemer, Bernhardswald, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/78 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/561 (2013.01); H01L 21/768 (2013.01); H01L 21/78 (2013.01); H01L 23/3107 (2013.01); H01L 23/481 (2013.01); H01L 24/96 (2013.01); H01L 25/50 (2013.01); H01L 21/568 (2013.01); H01L 23/562 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A method of producing a semiconductor device is provided. The method includes: providing a semiconductor wafer, the wafer including an upper layer of a semiconductor material, an inner etch stop layer and a lower layer; forming a plurality of functional areas in the upper layer; performing a selective first etch process on the upper layer so as to separate the plurality of functional areas from each other by trenches etched through the upper layer, the first etch process being substantially stopped by the inner etch stop layer; and removing the lower layer by a second etch process, the second etch process being substantially stopped by the inner etch stop layer.


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