The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2018

Filed:

Dec. 09, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sarathy Jayakumar, Portland, OR (US);

Mohan J. Kumar, Aloha, OR (US);

Eswaramoorthi Nallusamy, Puyallup, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/02 (2006.01); G06F 12/0868 (2016.01); G06F 12/0891 (2016.01); G06F 12/0866 (2016.01); G06F 12/0804 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 12/0868 (2013.01); G06F 12/0804 (2013.01); G06F 12/0866 (2013.01); G06F 12/0891 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/7203 (2013.01);
Abstract

Apparatus, systems, and methods to manage memory operations are described. A cache controller is provided comprising logic to receive a transaction to operate on a data element in a cache memory, determine whether the data element is to be stored in a nonvolatile memory by querying a source address decoder (SAD), and, in response to a determination that the data element is to be stored in the nonvolatile memory, to forward the transaction to a memory controller coupled to the nonvolatile memory, and, in response to a determination that the data element is not to be stored in the nonvolatile memory, to drop the transaction from a cache flush procedure of the cache controller. Additionally, the cache controller may receive a confirmation signal from the memory controller that the data element was stored in the nonvolatile memory, and return a completion signal to an originator of the transaction. The cache controller may also include logic to place a processor core in a low power state.


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