The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2018

Filed:

Jan. 04, 2017
Applicant:

General Electric Company, Schenectady, NY (US);

Inventors:

Victor Mario Torres, Clifton Park, NY (US);

Reza Ghandi, Niskayuna, NY (US);

David Alan Lilienfeld, Niskayuna, NY (US);

Avinash Srikrishnan Kashyap, Portland, OR (US);

Alexander Viktorovich Bolotnikov, Niskayuna, NY (US);

Assignee:

GENERAL ELECTRIC COMPANY, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/74 (2006.01); H01L 29/66 (2006.01); H01L 29/36 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 29/24 (2006.01); H01L 29/861 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66537 (2013.01); H01L 21/26586 (2013.01); H01L 21/30604 (2013.01); H01L 29/0661 (2013.01); H01L 29/0692 (2013.01); H01L 29/1608 (2013.01); H01L 29/2003 (2013.01); H01L 29/24 (2013.01); H01L 29/36 (2013.01); H01L 29/7424 (2013.01); H01L 29/7811 (2013.01); H01L 29/8618 (2013.01);
Abstract

The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.


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