The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2018
Filed:
Oct. 18, 2016
Sandisk Technologies Llc, Plano, TX (US);
Fabo Yu, San Ramon, CA (US);
Jayavel Pachamuthu, San Jose, CA (US);
Jongsun Sel, Los Gatos, CA (US);
Tuan Pham, San Jose, CA (US);
Cheng-Chung Chu, Milpitas, CA (US);
Yao-Sheng Lee, Tampa, FL (US);
Kensuke Yamaguchi, Yokkaichi, JP;
Masanori Terahara, Yokkaichi, JP;
Shuji Minagawa, Yokkaichi, JP;
SANDISK TECHNOLOGIES LLC, Plano, TX (US);
Abstract
Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.