The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2018

Filed:

May. 03, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Yong-Sang Cho, Hwaseong-si, KR;

Sang-Woo Pae, Seongnam-si, KR;

Hyun-Suk Chun, Yongin-si, KR;

Young-Seok Jung, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/58 (2006.01); H01L 23/31 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 24/02 (2013.01); H01L 23/585 (2013.01); H01L 24/94 (2013.01); H01L 23/3114 (2013.01); H01L 23/525 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/0237 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02235 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/94 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/141 (2013.01); H01L 2924/351 (2013.01);
Abstract

A semiconductor device comprises a semiconductor chip which includes at least one gate structure on a substrate, the gate structure including a first region, a second region different from the first region, and a third region between the first and the second region, a first redistribution layer on a top surface of the semiconductor chip, the first redistribution layer configured to electrically connect a first electrode pad of the semiconductor chip to a first solder ball and overlap the first region of the gate structure, a second redistribution layer on the top surface of the semiconductor chip, the second redistribution layer configured to electrically connect a second electrode pad of the semiconductor chip to a second solder ball and overlap the second region of the gate structure such that the third region is exposed, and an insulating layer on the first redistribution layer and the second redistribution layer.


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