The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2018

Filed:

Jun. 14, 2016
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

L. Scott Klingbeil, Chandler, AZ (US);

Colby Rampley, Phoenix, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 2221/68327 (2013.01); H01L 2223/5446 (2013.01);
Abstract

Method embodiments of wafer dicing for backside metallization are provided. One method includes: applying dicing tape to a front side of a semiconductor wafer, wherein the front side of the semiconductor wafer includes active circuitry; cutting a back side of the semiconductor wafer, the back side opposite the front side, wherein the cutting forms a retrograde cavity in a street of the semiconductor wafer, the retrograde cavity has a gap width at the back side of the semiconductor wafer, and the retrograde cavity has sidewalls with negative slope; depositing a metal layer on the back side of the semiconductor wafer, wherein the gap width is large enough to prevent formation of the metal layer over the retrograde cavity; and cutting through the street of the semiconductor wafer subsequent to the depositing the metal layer.


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