The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2018
Filed:
May. 13, 2015
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Jim Kardach, Saratoga, CA (US);
Nikos Kaburlasos, Rancho Cordova, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/406 (2006.01); G11C 7/10 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40618 (2013.01); G06F 12/0223 (2013.01); G06F 12/06 (2013.01); G06F 12/0607 (2013.01); G11C 7/1072 (2013.01); G11C 11/406 (2013.01); G11C 11/40622 (2013.01); G06F 2212/1028 (2013.01); Y02B 60/1225 (2013.01);
Abstract
Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.